A Low Complexity, High Speed, Regular and Flexible Reed Solomon Decoder for Wireless Communication

This paper proposes a low complexity, high speed, regular and flexible architecture for VLSI implementation of Reed Solomon decoder. With this architecture the error locator and error evaluator polynomials of the decoder can be computed in parallel and the same datapath can be reused to realize a partially pipelined parallel RS decoder. By architecture reuse the number of required resources for the RS decoder can be adjusted to a specific application, while maintaining internal parallel computation of each RS procedure. The resulting architecture contains one type of program element, which simplifies test and fabrication