Title :
Architecture Design for the Context Formatter in the H.264/AVC Encoder
Author_Institution :
Inst. of Radioelectonics, Warsaw Univ. of Technol.
Abstract :
Hardware accelerators for H.264/AVC using arithmetic coding require special approaches to achieve high throughputs. This paper proposes an efficient architecture for the context formatter that is a part of the H.264/AVC binary encoder. Five versions of the architecture are developed to match different throughputs. The implementation results show that the proposed versions of the context formatter match the performance of corresponding arithmetic coders
Keywords :
arithmetic codes; binary codes; video coding; AVC encoder; H.264 encoder; arithmetic coding; binary encoder; context formatter; hardware accelerators; Arithmetic; Automatic voltage control; Buffer storage; Clocks; Counting circuits; Encoding; Hardware; Registers; Throughput; Video compression;
Conference_Titel :
Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE
Conference_Location :
Prague
Print_ISBN :
1-4244-0185-2
DOI :
10.1109/DDECS.2006.1649573
