• DocumentCode
    2186621
  • Title

    Design of a Scalable Asynchronous Dataflow Processor

  • Author

    Lampinen, H. ; Perala, P. ; Vainio, O.

  • Author_Institution
    Inst. of Digital & Comput. Syst., Tampere Univ. of Technol.
  • fYear
    2006
  • fDate
    18-21 April 2006
  • Firstpage
    85
  • Lastpage
    86
  • Abstract
    This paper presents a scalable asynchronous dataflow processor. The main idea of the presented processor architecture is that the processing elements (PEs) are intelligent and can communicate directly with each other. A control element (CE) is used to solve possible conflicts between the data transferring of PEs and to control the execution of the program
  • Keywords
    asynchronous circuits; logic design; microprocessor chips; asynchronous dataflow processor; control elements; data transfer; processing elements; Asynchronous circuits; Centralized control; Circuit noise; Clocks; Computer architecture; Dynamic voltage scaling; Electromagnetic interference; Electronic design automation and methodology; Energy consumption; Power supplies;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE
  • Conference_Location
    Prague
  • Print_ISBN
    1-4244-0185-2
  • Type

    conf

  • DOI
    10.1109/DDECS.2006.1649581
  • Filename
    1649581
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2186621