Design of a scan line image processor chip

This paper describes a linear array image processor chip called the SliM-II image processor. The chip has 64 processing elements (PEs) connected by a linear array. In contrast to existing array processors, each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU, a data I/O, and an inter-PE communication operations simultaneously in an instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel data load/store between the register file and on-chip memory as in DSP chips. The SliM-II chip has been implemented, which contains about 1.5 million transistors in a 13.2×13.0 mm² die size and the package type is 208 pin PQ2. The performance estimation shows a significant improvement compared with existing array processors