Digit pipelined arithmetic for 3-D massively parallel optoelectronic circuits

A concept for a future integer arithmetic unit as well as a first implementation of the arithmetic unit´s core as smart pixel detector chip is presented. This architecture is well-suited for a realization with 3-D optoelectronic very large scale integrated (VLSI) circuits. Due to the use of optical interconnections running vertically to the circuit´s surface no pin limitation is given. This allows massively parallelism and a higher throughput performance than in all-electronic solutions. To exploit the potential of optical interconnections in VLSI systems efficiently well-adapted low-level algorithms and architectures have to be developed. This is demonstrated for a pipelined arithmetic unit using a redundant number representation. A gate layout for the optoelectronic circuits is given as well as a specification for the necessary optical interconnection scheme linking the circuits with free-space optics. It is shown that the throughput can be increased by a factor of 10 to 50 compared to current all-electronic processors by considering state-of-the-art optical and optoelectronic technology