Title :
Power-Constrained, Sessionless SOC Test Scheduling Based on Exploration of I-Schedule State-Space
Author_Institution :
Fac. of Inf. Technol., Brno Univ. of Technol.
Abstract :
In the paper, novel sessionless approach to test-schedulling is presented. It utilizes so-called STEPs during special random-search based scheduling algorithm. The algorithm explores the state-space of so-called i-schedules whereas an i-schedule is an integer-vector encoded test-schedule represented by n-touple of STEPs. Proposed algorithm tries to link tests to STEPs in such a way there are no resource sharing conflicts in the best-found test schedule and hopefully, test schedule constraints are met maximally at minimal time and TAM values
Keywords :
integrated circuit testing; logic testing; scheduling; state-space methods; system-on-chip; i-schedule state-space; integer-vector encoded test-schedule; random-search based scheduling algorithm; sessionless SOC test scheduling; system-on-chip; test schedule constraints; Biological cells; Energy consumption; Genetic algorithms; Information technology; Paper technology; Resource management; Scheduling algorithm; Space exploration; State-space methods; Testing;
Conference_Titel :
Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE
Conference_Location :
Prague
Print_ISBN :
1-4244-0185-2
DOI :
10.1109/DDECS.2006.1649604
