Design-for-Test of Asynchronous Networks-on-Chip

Author

Tran, Xuan-Tu ; Beroulle, Vincent ; Durupt, Jean ; Robach, Chantal ; Bertrand, Francois

Author_Institution

CEA/LETI, Grenoble

fYear

2006

fDate

18-21 April 2006

Firstpage

161

Lastpage

165

Abstract

Thanks to many advantages, asynchronous circuits have been used to solve the interconnect problems faced by system-on-chip (SoC) designers. Some asynchronous networks-on-chip (NoCs) architectures are proposed for the communication within SoCs, but lack methodology and support for manufacturing test to ensure these communication architectures work correctly. In this paper, we present an innovative asynchronous DfT architecture that allows to test the asynchronous communication network architectures, as well as the synchronous computing resources and the asynchronous/synchronous network interfaces on the asynchronous NoC-based SoCs. This asynchronous DfT architecture is implemented in quasi delay insensitive (QDI) asynchronous circuits and uses an area of about 20 * 8 Kgates in an asynchronous NoC-based SoC of 4.5 Mgates without memories

Keywords

asynchronous circuits; design for testability; integrated circuit testing; logic testing; network-on-chip; asynchronous NoC-based SoC; asynchronous communication network architectures; asynchronous network interfaces; asynchronous networks-on-chip; design for test; quasidelay insensitive asynchronous circuits; synchronous computing resources; synchronous network interfaces; Asynchronous circuits; Asynchronous communication; Circuit testing; Computer architecture; Computer interfaces; Design for testability; Integrated circuit interconnections; Manufacturing; Network-on-a-chip; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE

Conference_Location

Prague

Print_ISBN

1-4244-0185-2

Type

conf

DOI

10.1109/DDECS.2006.1649605

Filename

1649605