• DocumentCode
    2187445
  • Title

    Low power scheduling with resources operating at multiple voltages

  • Author

    Shiue, Wen-Tsong ; Chakrabarti, Chaitali

  • Author_Institution
    Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA
  • Volume
    2
  • fYear
    1998
  • fDate
    31 May-3 Jun 1998
  • Firstpage
    437
  • Abstract
    This paper presents (i) a resource constrained scheduling scheme and (ii) a latency-constrained scheduling scheme that minimize power consumption for the case when the resources operate at multiple voltages. The resource-constrained scheduling reduces the power consumption by maximally utilizing resources operating at reduced voltages and at the same time reducing the latency. The latency-constrained scheduling scheme reduces the power consumption by assigning as many nodes (of the data flow graph) as possible to the resources operating at reduced voltages. Two cases have been studied: one in which the possible operating voltages are 5 V and 3.3 V, and the other in which the operating voltages are 5 V, 3.3 V and 2.4 V. Experiments with some HLS benchmark examples show that the proposed schemes achieve significant power reduction
  • Keywords
    VLSI; circuit CAD; data flow graphs; high level synthesis; integrated circuit design; scheduling; DFG; data flow graph; latency-constrained scheduling scheme; low power scheduling; multiple voltages; power consumption minimisation; power reduction; resource constrained scheduling scheme; Algorithm design and analysis; Delay; Dynamic programming; Energy consumption; Flow graphs; Iterative algorithms; Power system reliability; Processor scheduling; Scheduling algorithm; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
  • Conference_Location
    Monterey, CA
  • Print_ISBN
    0-7803-4455-3
  • Type

    conf

  • DOI
    10.1109/ISCAS.1998.706970
  • Filename
    706970