Embedded Self Repair by Transistor and Gate Level Reconfiguration

Author

Kothe, Rene ; Vierhaus, Heinrich T. ; Coym, Torsten ; Vermeiren, Wolfgang ; Straube, Bernd

Author_Institution

Brandenburg Univ. of Technol. Cottbus

fYear

2006

fDate

18-21 April 2006

Firstpage

208

Lastpage

213

Abstract

Technology forecasts predict that nanometer IC technologies do not yield large chip areas without non-functional transistors. Mechanism of redundancy and re-organization for self-repair at the transistor and gate level are required, which can effectively handle realistic fault effects in CMOS logic circuits

Keywords

CMOS logic circuits; embedded systems; fault diagnosis; integrated circuit testing; logic testing; CMOS logic circuits; embedded self repair; gate level reconfiguration; nanometer IC technologies; realistic fault effects; transistor level reconfiguration; CMOS logic circuits; CMOS technology; Circuit faults; Design automation; Field programmable gate arrays; Logic circuits; Logic testing; Redundancy; Sections; Technology forecasting;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE

Conference_Location

Prague

Print_ISBN

1-4244-0185-2

Type

conf

DOI

10.1109/DDECS.2006.1649613

Filename

1649613

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2187449