DocumentCode :
2187521
Title :
Optimal Memory Address Seeds for Pattern Sensitive Faults Detection
Author :
Yarmolik, S.V. ; Sokol, B.
Author_Institution :
Belarusian State Univ. of Informatics & Radioel., Bialystok Univ. of Technol.
fYear :
2006
fDate :
18-21 April 2006
Firstpage :
218
Lastpage :
219
Abstract :
The goal of this paper is to propose a new technique for memory testing based on transparent memory march tests (van de Goor, 1991 and Nicolaidis, 1996). This paper deals with memory pattern sensitive faults detection problem. It shows the efficiency of multiple runs of march tests for memory passive pattern sensitive faults detection and analyzes the optimal address seeds for multiple march test runs. This paper provides only short fragment of carried researches. All results can be found in extended version of this paper
Keywords :
fault diagnosis; integrated circuit testing; integrated memory circuits; logic testing; memory pattern sensitive faults detection; memory testing; optimal memory address seeds; passive pattern sensitive faults detection; transparent memory march tests; Counting circuits; Equations; Fault detection; Informatics; Pattern analysis; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE
Conference_Location :
Prague
Print_ISBN :
1-4244-0185-2
Type :
conf
DOI :
10.1109/DDECS.2006.1649616
Filename :
1649616
Link To Document :
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