Title :
SOC Diagnostic Design Using RESPIN Architecture
Author :
Mader, Z. ; Jarkovsky, M.
Author_Institution :
Liberec Tech. Univ.
Abstract :
This paper describes realization of a project that is concerned with a diagnostic system of a SOC. The diagnostic system used RESPIN architecture is based on the IEEE 1500 standard and allows testing of cores by compressed test patterns. The patterns for certain core under test are decompressed in the scan chains of the other idle core during the test time. The compressed form of the test patterns is prepared by the algorithm COMPAS and stored in the memory of the SOC. The diagnostic system was implemented to the FPSLIC AT94K circuit that contain FPGA for cores, processor for control test procedure and the memory for storing the compressed test data in one system chip
Keywords :
IEEE standards; automatic test pattern generation; boundary scan testing; integrated circuit design; system-on-chip; COMPAS algorithm; FPGA; IEEE 1500 standard; RESPIN architecture; SOC diagnostic design; SOC memory; compressed test patterns; core testing; diagnostic system; scan chains; system-on-chip; Bandwidth; Circuit testing; Computer architecture; Field programmable gate arrays; Multiplexing; Postal services; Process control; Random access memory; Read-write memory; System testing;
Conference_Titel :
Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE
Conference_Location :
Prague
Print_ISBN :
1-4244-0185-2
DOI :
10.1109/DDECS.2006.1649626
