DocumentCode
2187735
Title
Dynamic Decimal Adder Circuit Design by using the Carry Lookahead
Author
You, Younggap ; Kim, Yong Dae ; Choi, Jong Hwa
Author_Institution
Dept. of Inf. Commun. Eng., Chungbuk Nat. Univ.
fYear
2006
fDate
18-21 April 2006
Firstpage
242
Lastpage
244
Abstract
This paper presents a carry look ahead (CLA) circuitry design based on dynamic circuit aiming at delay reduction in addition of BCD coded decimal numbers. The performance of the proposed dynamic decimal adder is analyzed demonstrating its speed improvement. Timing simulation on the proposed decimal addition circuit employing 0.25 mum CMOS technology yields the worst case delay of 622 ns
Keywords
CMOS logic circuits; adders; carry logic; logic design; 0.25 micron; 622 ns; BCD coded decimal numbers; CLA circuitry design; CMOS technology; carry look ahead; dynamic decimal adder; Added delay; Adders; CMOS technology; Calculators; Circuit synthesis; Equations; Finite wordlength effects; Laboratories; Performance analysis; Propagation delay;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE
Conference_Location
Prague
Print_ISBN
1-4244-0185-2
Type
conf
DOI
10.1109/DDECS.2006.1649627
Filename
1649627
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