DocumentCode :
2187744
Title :
Channel allocation, power budget and bit error rate in hierarchical optical ring interconnection network (HORN)
Author :
Jones, Thomas S. ; Louri, Ahmed
Author_Institution :
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
fYear :
1998
fDate :
15-17 Jun 1998
Firstpage :
123
Lastpage :
130
Abstract :
Recent advances in computer processing speeds have resulted in a parallel processing environment in which the interconnection networks (INs) themselves are the limiting factor in terms of performance. Larger and faster INs can be implemented optically subject to the current limitation in the number of wavelengths imposed by optical switch and filter technology if the INs are arranged hierarchically, i.e. if the processing nodes are arranged in clusters and these clusters are connected together special routing nodes at one or more higher levels. HORN uses optically connected rings as the basic building blocks and connects these rings using an optical tree. Three key issues facing HORN are addressed in this paper: dynamic channel allocation (DCA), optical power budget (OPE) and bit error rate (BER). Four approaches to DCA are evaluated and a design trade-off is performed between them. The first two are taken from the literature while the last two are proposed here and exploit the multiple paths available in a hierarchical network. The evaluation of OPE and BER shows that HORN is feasible and practical when optical amplification is used at the initial signal insertion point for transmissions at higher levels in the hierarchy
Keywords :
multiprocessor interconnection networks; optical interconnections; HORN; bit error rate; channel allocation; hierarchical optical ring interconnection network; interconnection networks; optical tree; optically connected rings; parallel processing environment; power budget; Bit error rate; Channel allocation; Computer networks; Concurrent computing; Limiting; Multiprocessor interconnection networks; Optical filters; Optical interconnections; Optical switches; Parallel processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Massively Parallel Processing, 1998. Proceedings. Fifth International Conference on
Conference_Location :
Las Vegas, NV
Print_ISBN :
0-8186-8572-7
Type :
conf
DOI :
10.1109/MPPOI.1998.682135
Filename :
682135
Link To Document :
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