Multiple-Vector Column-Matching BIST Design Method

Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo-random code words into deterministic test patterns pre-computed by an ATPG tool. The column-matching algorithm is used to design the decoder. Using this algorithm, maximum of decoder outputs is tried to be matched with the decoder inputs, yielding the outputs be implemented as wires, thus without any logic. The newly proposed enhancement consists in a major generalization of the method. The ATPG possibility of generating more than one test vectors for one fault is exploited, yielding smaller area overhead. The complexity of the resulting BIST logic reduction is evaluated for some of the ISCAS benchmarks