Title :
Link sharing scheme for fault tolerant systolic arrays based on mixed spatial-temporal triple modular redundancy
Author :
Kaneko, Mineo ; Miyauchi, Hiroyuki ; Park, Choon-Sik
Author_Institution :
Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan
Abstract :
A systematic procedure to configure fault-tolerant systolic arrays based on Triple Modular Redundancy in mixed spatial-temporal domain is proposed. While the triplication of the original dependence graph brings complicated data communication, unforced and forced link sharing schemes are introduced and detailed design procedures utilizing them for reducing link complexity are proposed
Keywords :
VLSI; fault tolerant computing; graph theory; redundancy; systolic arrays; complicated data communication; dependence graph; fault tolerant systolic arrays; forced link sharing schemes; link complexity; link sharing scheme; mixed spatial-temporal triple modular redundancy; unforced sharing schemes; Algorithm design and analysis; Arithmetic; Data communication; Data processing; Fault tolerance; Processor scheduling; Strontium; Systolic arrays; Timing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1996., IEEE Asia Pacific Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-3702-6
DOI :
10.1109/APCAS.1996.569316
