Title :
FITTest BENCH06: A New Set of Benchmark Circuits Reflecting Testability Properties
Author :
Pecenka, T. ; Kotasek, Z. ; Sekanina, L.
Author_Institution :
Fac. of Inf. Technol., Brno Univ. of Technol.
Abstract :
In the paper, the FITTest_BENCH06 set of synthetic benchmark circuits is presented for the evaluation of diagnostic methods and tools. The structure of benchmark circuits together with their diagnostic properties is described. The set consists of 31 circuits at various levels of complexity (2000, 10000, 28000, 100000, 150000 and 300000 gates). Four circuits with different diagnostic properties are available for each level of circuit complexity (fault coverage is approx. 0%, 33%, 66% and 100%). The benchmark circuits are available both at the register transfer level and the gate level. In addition to the benchmark set, a method is described that was used to develop benchmark circuits with required complexity and diagnostic properties
Keywords :
benchmark testing; circuit CAD; fault simulation; FITTest_BENCH06; circuit complexity; diagnostic methods; diagnostic tools; gate level; register transfer level; synthetic benchmark circuits; Automatic test pattern generation; Automatic testing; Benchmark testing; Circuit faults; Circuit synthesis; Circuit testing; Flexible printed circuits; High level synthesis; Information technology; Logic testing;
Conference_Titel :
Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE
Conference_Location :
Prague
Print_ISBN :
1-4244-0185-2
DOI :
10.1109/DDECS.2006.1649636
