VLSI design of a CORDIC-based derotator

A derotator VLSI which removes the frequency and phase errors of a received signal in digital receivers was developed using a CORDIC algorithm. The CORDIC circuit directly rotates the input signal according to the phase error information, thus is much simpler than the conventional derotator architecture which consists of a DDFS (Direct Digital Frequency Synthesizer) and a complex multiplier. In order to improve the operating speed without employing the pipelining, a fast direction sequence generation method that exploits the linearity of the tangent function in small angles is utilized. The newly employed direction sequence generation method needs only about a third of the iterative computations when compared with the conventional CORDIC algorithm. The chip was designed and implemented using a 0.6 μm triple metal CMOS process by the full custom layout method. The whole chip size is 6.8 mm² and the operating frequency which is higher than 25 MHz is achieved