An integrated CAD tool for ASIC implementation of multiplierless FIR filters with common sub-expression elimination optimization

This paper presents an integrated computer aided design (CAD) tool for the ASIC implementation of multiplierless FIR digital filters with common sub-expression elimination (CSE) optimization. The main functions in the design flow of FIR filters for specified applications, including coefficient calculation and quantization, common sub-expression optimization and hardware description language (HDL) code auto-generation, are combined in this tool. We propose an applied intermedial representation (IR), which is the key for the integration of CSE optimization and HDL code auto-generation, to denote the circuit structure resulted from the application of CSE technique. The application of this tool in the ASIC implementation of multiplierless FIR filters can realize the design automation and shorten the time for design significantly; what is more, experiment results show that the desired FIR filters are optimized efficiently in several aspects such as area, power dissipation and speed.