Title :
High performance sub-100 nm Si thin-film transistors by Pattern-controlled crystallization of Thin channel layer and High temperature annealing
Author :
Jian Gu ; Wei Wu ; Chou, S.Y.
Author_Institution :
Dept. of Electr. Eng., Princeton Univ., NJ, USA
Abstract :
In this work, we report the fabrication of high performance thin-film transistors (TFTs) down to sub-100 nm regime using Pattern-controlled crystallization of Thin channel layer and High temperature annealing (PaTH). High temperature is used to improve the film quality. Thin body thickness (Tsi) is used to suppress the short channel effects. The devices showed superior switching properties and device-to-device uniformity over conventional poly-Si TFTs.
Keywords :
annealing; crystallisation; elemental semiconductors; silicon; thin film transistors; 100 nm; Si; Si thin film transistor; device-to-device uniformity; high temperature annealing; pattern-controlled crystallization; short channel effect; switching properties; thin channel layer; Annealing; Crystallization; Fabrication; Grain boundaries; Immune system; Laboratories; Silicon on insulator technology; Statistics; Temperature; Thin film transistors;
Conference_Titel :
Device Research Conference, 2002. 60th DRC. Conference Digest
Conference_Location :
Santa Barbara, CA, USA
Print_ISBN :
0-7803-7317-0
DOI :
10.1109/DRC.2002.1029501
