Reliability and ESD for high voltage LDMOS with SenseFET

This paper presents the structure and method of effective ESD protection and reliability in high voltage LDMOS with Sense Source (SenseFET) which is newly proposed 1-chip process for smart power ICs. This structure and method have been investigated experimentally and theoretically by employing two-dimensional process and device simulators. The cause of failure turned out to be Sense Source which is failed on reliability and ESD experiment more than LDMOS itself. The distance between the drain pad and the Sense Source must be long enough and Sense Source must be closely located with a lot of Ground contact if possible.