3D silicon-based packaging for light emitting diodes

The three-dimensional (3D) light-emitting diodes (LEDs) integration package based on silicon with through silicon vias (TSV) attracts a lot of attention because of a better performance, lighter package, and higher integration density. Two main kinds of LED chip including conventional chip (CC) and vertical chip (VC) encapsulated in silicon platform with and without a reflector cup are analyzed through simulation to understand the optical and thermal characteristics of the module. The results show that the light extraction efficiency (LEE) is more dependent on the type of the chip instead of the structural parameters of the reflector cup. However, it has a significant effect on the far-field pattern of the package module. The thermal analyses show that the temperature distribution is uniform due to the high thermal conductivity and convection coefficient. Mismatch of thermal expansion coefficients (CTE) between TSV-full-filled copper of lOOum-thickness and silicon causes large thermal stress, the maximum von Mises stress reaching 272MPa, which would be decreased by 11.0% through half filling TSV with the copper of 20um-thickness.