DocumentCode
2188791
Title
Variation-Tolerant Motion Estimation Architecture
Author
Varatkar, Girish V. ; Shanbhag, Naresh R.
Author_Institution
Coordinated Science Laboratory/ECE Department, University of Illinois at Urbana-Champaign, 1308 W Main St., Urbana IL 61801
fYear
2007
fDate
17-19 Oct. 2007
Firstpage
126
Lastpage
131
Abstract
In this paper, we study the trade-off between energy-efficiency and variation-tolerance of an error-resilient motion estimation architecture. Error-resiliency is incorporated via algorithmic noise-tolerance (ANT) where an input subsampled replica (ISR) of the main sum-of-absolute-difference(MSAD) block is employed for detecting and correcting errors in the MSAD block. This architecture is referred to as ISR-ANT. In the presence of process variations, the average peak signal-to-noise ratio (PSNR) of ISR-ANT architecture increases by up to 1.8dB over that of the conventional architecture in 130nm IBM process technology. Furthermore, the PSNR variation is also reduced by 7Ã over that of the conventional architecture at the slow corner while achieving a power reduction of 33%.
Keywords
Adders; Circuits; Energy consumption; Energy efficiency; Error correction; Motion estimation; Signal processing; Threshold voltage; Timing; Video compression; error resiliency; process variation;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems, 2007 IEEE Workshop on
Conference_Location
Shanghai, China
ISSN
1520-6130
Print_ISBN
978-1-4244-1222-8
Electronic_ISBN
1520-6130
Type
conf
DOI
10.1109/SIPS.2007.4387531
Filename
4387531
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