Low Power Multipliers Using Enhenced Row Bypassing Schemes

In this paper, we proposed two novel low power multipliers based on enhanced row bypassing schemes. The essence of the power saving idea is eliminating unnecessary computation via signal bypassing. In an array multiplier, futile computations occur on those columns or rows of adder corresponding to zero bits in the input operands. Previous designs resort to input gating and output multiplexing to accomplish signal bypassing. The proposed designs, however, successfully resolve the adverse DC power consumption problem due to voltage loss in gated signals and implement the multiplexing mechanism cleverly via clock CMOS (C²MOS) circuitry. Two versions of the design are proposed with one emphasizing on maximizing power saving and the other focusing on reduced circuit complexity. The circuit overheads of both designs are confined to 23.4% and 12.8%, respectively. The proposed designs also achieve better and consistent power saving than previous work under a wide range of Vdd and the power saving can be as high as 17%.