Title :
Architecture Design of the Double-Mode Binarization for High-Profile H.264/AVC Compression
Author :
Pastuszak, Grzegorz
Author_Institution :
Institute of Radioelectronics, Warsaw University of Technology, Warsaw, Poland
Abstract :
The efficiency of hardware video encoders depends on all modules embedded in the processing path. This paper presents the architecture of the H.264/AVC binarization unit, which is a part of the last stage of the video coder. The module supports CABAC and CAVLC modes and conforms to H.264/AVC High Profile. The architecture saves a considerable amount of hardware resources since two coding modes share the same logic and storage elements. For both modes, the architecture achieves the similar throughput able to support HDTV.
Keywords :
Automatic voltage control; Computer architecture; Field programmable gate arrays; HDTV; Hardware; Logic; Streaming media; Throughput; Video compression; Video sharing; FPGA; H.264/AVC; VLSI architecture; Video compression;
Conference_Titel :
Signal Processing Systems, 2007 IEEE Workshop on
Conference_Location :
Shanghai, China
Print_ISBN :
978-1-4244-1222-8
Electronic_ISBN :
1520-6130
DOI :
10.1109/SIPS.2007.4387540
