Efficient DSP implementation of an adaptive line enhancer based on the convex combination of two IIR filters

An adaptive line enhancer is a self-tuning filter which attempts to retrieve a sinusoid buried in noise. Generally speaking, there is a trade-off between convergence speed and steady-state error. One method to address this is to use a variable step size algorithm, with a large step size for acquisition, and a smaller step size for improved steady-state performance. An alternate topology is based on the convex combination of two adaptive filters; a fast filter handles acquisition, while a slower filter is used to minimize error. The authors recently introduced an adaptive line enhancer based on the convex combination of two IIR filters, which achieved both fast tracking and good steady-state performance, but at an increase in computational complexity. However, the dual structure of this filter lends itself well to parallel software execution. This paper examines methods that can be used to achieve an efficient hardware implementation of the algorithm.