Title :
Tunneling through multi-layer gate dielectrics - an analytical model
Author :
Polishchuk, I. ; Yee-Chia Yeo ; Tsu-Jae King ; Chenming Hu
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
We propose an analytical direct-tunneling model for multilayer gate dielectrics. This model predicts the amount of gate leakage current as a function of equivalent oxide thickness of the gate dielectric stack and the composition of the stack. This simple model is a useful tool in the development of future CMOS gate dielectric stacks.
Keywords :
CMOS integrated circuits; WKB calculations; dielectric thin films; integrated circuit modelling; leakage currents; multilayers; tunnelling; CMOS gate dielectric stacks; SiO/sub 2/; WKB approximation; analytical direct-tunneling model; dielectric stack composition; gate dielectric stack equivalent oxide thickness; gate leakage current prediction; multi-layer gate dielectrics; Analytical models; CMOS integrated circuits; Dielectrics; Electrons; Frequency; Leakage current; Predictive models; Semiconductor device modeling; Tunneling; Voltage;
Conference_Titel :
Device Research Conference, 2002. 60th DRC. Conference Digest
Conference_Location :
Santa Barbara, CA, USA
Print_ISBN :
0-7803-7317-0
DOI :
10.1109/DRC.2002.1029537
