Title :
Conditional pre-charge techniques for power-efficient dual-edge clocking
Author :
Nedovic, Nikola ; Aleksic, Marko ; Oklobdzija, Vojin G.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
Abstract :
A new dual edge-triggered flip-flop that saves power by inhibiting transitions of the nodes that are not used to change the state is presented. The proposed flip-flop is 12% faster with 10% lower energy-delay product for 50% data activity, as compared to the previously published dual edge-triggered storage elements. This was confirmed by simulation using 0.18μm process, 1.8V power supply, and clock frequency of 250MHz. This flip-flop is particularly suitable for low-power applications.
Keywords :
clocks; delays; flip-flops; low-power electronics; sequential circuits; 0.18 micron; 1.8 V; 250 MHz; clock frequency; conditional pre-charge techniques; dual edge-triggered flip-flop; energy-delay product; low-power applications; power-efficient dual-edge clocking; sequential circuits; Clocks; Energy consumption; Flip-flops; Frequency; Laboratories; Power engineering and energy; Power engineering computing; Systems engineering and theory; Timing; Uncertainty;
Conference_Titel :
Low Power Electronics and Design, 2002. ISLPED '02. Proceedings of the 2002 International Symposium on
Print_ISBN :
1-5811-3475-4
DOI :
10.1109/LPE.2002.146709
