Neural core module for embedded intelligence

Author

Diepenhorst, M. ; Haseborg, H. Ter ; Nijhuis, J.A.G. ; Spaanenburg, L.

Author_Institution

Dept. of Comput. Sci., Groningen Univ., Netherlands

Volume

2

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

462

Abstract

A multiplication unit is proposed that allows for an efficient computation of products of 32-, 16- and 8-bit fixed point numbers. In the latter two modes of operation, two resp. four multiplications are executed in parallel. The proposed unit implements multiplication according to the DIGILOG principle and is designed to operate on a 100 Mhz clock in a 0.8 mm CMOS technology. The design of the unit is motivated by the potential benefits to be gained from a digital platform that integrates the emulation and training of neural networks with pre-processing of the signals that they process. Efficient realization of the multiplication operation is a major requirement of such a device

Keywords

CMOS digital integrated circuits; digital arithmetic; multiplying circuits; neural chips; 0.8 micron; 100 MHz; 16 bit; 32 bit; 8 bit; CMOS digital circuit; DIGILOG arithmetic; embedded intelligence; emulation; fixed point number; neural core module; neural network; parallel multiplication; signal pre-processing; training; Arithmetic; CMOS technology; Clocks; Emulation; Equations; Intelligent sensors; Neural networks; Signal design; Signal processing; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.706976

Filename

706976