DocumentCode
2189415
Title
Montgomery Modular Multiplication Algorithm on Multi-Core Systems
Author
Fan, Junfeng ; Sakiyama, Kazuo ; Verbauwhede, Ingrid
Author_Institution
Katholieke Universiteit Leuven, ESAT/SCD-COSIC, Kasteelpark Arenberg 10, B-3001 Leuven-Heverlee, Belgium
fYear
2007
fDate
17-19 Oct. 2007
Firstpage
261
Lastpage
266
Abstract
In this paper, we investigate the efficient software implementations of theMontgomery modular multiplication algorithm on amulti-core system. AHW/SW co-design technique is used to find the efficient system architecture and the instruction scheduling method. We first implement the Montgomery modular multiplication on a multi-core systemwith general purpose cores. We then speed up it by adopting the Multiply-Accumulate (MAC) operation in each core. As a result, the performance can be improved by a factor of 1.53 and 2.15 when 256-bit and 1024-bit Montgomery modular multiplication being performed, respectively.
Keywords
Computer architecture; Concurrent computing; Control system synthesis; Digital signal processing; Hardware; Processor scheduling; Software algorithms; Software performance; Systolic arrays; VLIW; Montgomery Modular Multiplication; Multi-core; Parallel Architectures;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems, 2007 IEEE Workshop on
Conference_Location
Shanghai, China
ISSN
1520-6130
Print_ISBN
978-1-4244-1222-8
Electronic_ISBN
1520-6130
Type
conf
DOI
10.1109/SIPS.2007.4387555
Filename
4387555
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