Spatial Feature Based Video Scaling Scheme and its FPGA Implementation for Video Standards Conversion

In many digital image/video processing applications resolution 1 enhancement naturally arises as a problem of high practical value. Typically, increasing spatial resolution through modifications in the imaging system is not a feasible option, and post-processing algorithms designed to enhance resolution of the acquired image/video signal prove beneficial. In this work, we analyze recent work on pixel classification based resolution enhancement, namely, resolution synthesis, and discuss its applicability to low complexity customer grade display systems. In the light of our observations, we point out certain short-comings of resolution synthesis, and propose a modified scheme to improve its performance under certain conditions. We present an FPGA implementation of the proposed algorithm, and provide a computational complexity analysis. The resulting hardware design is tested for a standards conversion application where 480×720 progressive frames are scaled to 720×1280 progressive at 60 frames per second.