Self-calibrating clock distribution with scheduled skews

This paper presents a self-calibrating clock distribution scheme that dynamically compensates manufacturing and environmental variations to minimize unintentional clock skews and employs non-zero intentional skews to improve system performance. The tracking process is implemented with an all-digital phase-locked loop and has been verified through a prototype chip. Test results confirm the theoretical predictions that the absolute value of unintentional skew is limited to Δ, which is the resolution of the sampling and compensation circuitry