Design of High Speed Cavlc Decoder for H.264/AVC

In this paper, we propose a high speed CAVLC (Context-based Adaptive Variable Length Coding) decoder for H.264/AVC. The previous hardware architectures perform five steps in series to obtain the syntax elements to restore the residual and the codeword length to get next input bitstream (we call it ´valid bits´). Since several cycles are required for the process of getting the valid bits and it has to be iterated several times during CAVLC process, the decoding time is increased. This paper proposes two techniques to reduce the computational cycles for valid bits. One is an improved reduced decoding step from five to four by combining total_coeff step and trailing_ones step into one step. The other is to get the valid bits directly by shifting additional shifter register instead of using controller and accumulator. By adopting these two techniques, the required processing time was reduced by 26% compared with previous architectures. It was designed in a hardware description language and total logic gate count was 14.2k using 0.18um standard cell library.