Design of a branch-based 64-bit carry-select adder in 0.18 μm partially depleted SOI CMOS

Author

Nève, Amaury ; Flandre, Denis ; Schettler, Helmut ; Ludwig, Thomas ; Hellner, Gerhard

Author_Institution

Lab. de Microelectronique, Univ. Catholique de Louvain, Louvain-la-Neuve, Belgium

fYear

2002

fDate

2002

Firstpage

108

Lastpage

111

Abstract

The paper presents the design of a 64-bit carry-select adder in Branch-Based Logic, a static design style that minimizes the internal node capacitances. This feature is used to lower the dynamic power dissipation, while maintaining good speed performances. The experimental realization of the adder demonstrates an overall delay of 720 ps while only dissipating 96 mW at 1 GHz. The fabrication is based on the 0.18 μm IBM CMOS8S2 SOI technology, which uses partially depleted transistors and copper metallization.

Keywords

CMOS logic circuits; adders; logic design; low-power electronics; silicon-on-insulator; 0.18 micron; 1 GHz; 64 bit; 720 ps; 96 mW; branch-based logic; carry-select adder; copper metallization; delay; dynamic power dissipation; internal node capacitance; partially depleted SOI CMOS; static design; Adders; CMOS logic circuits; CMOS technology; Delay; Logic design; MOS devices; Parasitic capacitance; Power dissipation; Silicon on insulator technology; Vehicle dynamics;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2002. ISLPED '02. Proceedings of the 2002 International Symposium on

Print_ISBN

1-5811-3475-4

Type

conf

DOI

10.1109/LPE.2002.146721

Filename

1029565