DocumentCode
2189959
Title
Multilayer tunneling barriers for nonvolatile memory applications
Author
Blomme, P. ; Govoreanu, B. ; Rosmeulen, M. ; Van Houdt, J. ; De Meyer, K.
Author_Institution
STDI Div., IMEC, Leuven, Belgium
fYear
2002
fDate
24-26 June 2002
Firstpage
153
Lastpage
154
Abstract
A tunnel barrier consisting of two materials with different dielectric constant is demonstrated to show that improved programming and/or erasing performance is obtained compared to conventional oxide layers. It is also shown that charge trapping is not a showstopper for the application of such stacks in floating gate nonvolatile memory devices.
Keywords
EPROM; MOS capacitors; dielectric thin films; flash memories; tunnelling; EEPROM; SiO/sub 2/-ZrO/sub 2/; SiO/sub 2//ZrO/sub 2/ stacks; capacitors; charge trapping; erasing performance; flash memory; floating gate nonvolatile memories; multilayer tunneling barriers; nonvolatile memory applications; programming performance; Capacitors; Dielectric constant; EPROM; High K dielectric materials; Lead compounds; Low voltage; Nonhomogeneous media; Nonvolatile memory; Testing; Tunneling;
fLanguage
English
Publisher
ieee
Conference_Titel
Device Research Conference, 2002. 60th DRC. Conference Digest
Conference_Location
Santa Barbara, CA, USA
Print_ISBN
0-7803-7317-0
Type
conf
DOI
10.1109/DRC.2002.1029569
Filename
1029569
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