DocumentCode :
2190169
Title :
GPU Accelerated VLSI Design Verification
Author :
Yangdong Deng
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
fYear :
2010
fDate :
June 29 2010-July 1 2010
Firstpage :
1213
Lastpage :
1218
Abstract :
Today´s Very Large Scale Integrated-Circuit (VLSI) designs require intensive verification effort. However, traditional sequential verification solutions could no longer provide the scalability for future large designs. The so-called verification gap hinders the development of future VLSI products. In this paper, we review our recent works on accelerating typical VLSI verification tasks with modern GPUs. Our works prove that the potential of GPUs can be effectively unleashed through designing efficient data parallel algorithms and/or re-structuring existing sequential algorithms.
Keywords :
VLSI; computer graphic equipment; coprocessors; electronic design automation; formal verification; parallel algorithms; VLSI design verification; data parallel algorithms; graphical processing unit; sequential algorithms; verification gap; very large scale integrated circuit; Computational modeling; Graphics processing unit; Integrated circuit modeling; Logic gates; Memory management; Sparse matrices; Timing; GPU; SAT; Simulation; Timing analysis; VLSI; Verification;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer and Information Technology (CIT), 2010 IEEE 10th International Conference on
Conference_Location :
Bradford
Print_ISBN :
978-1-4244-7547-6
Type :
conf
DOI :
10.1109/CIT.2010.219
Filename :
5577890
Link To Document :
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