Noise behavior of MOSFETs fabricated in 0.5 μm fully-depleted (FD) silicon-on-sapphire (SOS) CMOS in weak, moderate,, and strong inversion

This paper presents a summary of the measured noise behavior of CMOS MOSFETs fabricated in a 0.5 μm fully-depleted (FD) silicon-on-sapphire (SOS) process. SOS CMOS technology provides an alternative to standard bulk CMOS processes for high-density detector front-end electronics due to its inherent radiation tolerance. In this paper, the noise behavior of SOS devices will be presented and discussed with reference to device inversion coefficient (IC). The concept of inversion coefficient will be introduced and the results of SOS device noise measurements in weak, moderate, and strong inversion will be presented and compared for devices with gate lengths of 0.5 μm to 4 μm. Details of the noise measurement system will be provided including specifics of the measurement approach and custom circuits used for device biasing. This work will provide a thorough presentation of measured SOS device noise as a function of inversion coefficient. In addition, strategies for device biasing and sizing to obtain optimum noise performance will be presented encouraging more widespread use of SOS integrated circuits in high-density detector applications.