• DocumentCode
    2190459
  • Title

    VLSI architectures of divider for finite field GF(2m)

  • Author

    Wei, Shyue Win

  • Author_Institution
    Dept. of Electr. Eng., Chung-Hua Univ., Taiwain, China
  • Volume
    2
  • fYear
    1998
  • fDate
    31 May-3 Jun 1998
  • Firstpage
    482
  • Abstract
    A cellular-array power-sum circuit for GF(2m) is presented. According to the basic cellular-array power-sum circuit, several VLSI architectures that can be used to compute inversions and divisions over GF(2m) are proposed. Both computation speed and circuit complexity of the presented new divider can be improved by comparing with existing systolic circuits
  • Keywords
    VLSI; cellular arrays; digital arithmetic; dividing circuits; error correction codes; VLSI architectures; cellular-array power-sum circuit; circuit complexity; computation speed; divider; finite field; inversions; Arithmetic; Circuits; Complexity theory; Computer architecture; Decoding; Error correction codes; Galois fields; Polynomials; Power engineering computing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
  • Conference_Location
    Monterey, CA
  • Print_ISBN
    0-7803-4455-3
  • Type

    conf

  • DOI
    10.1109/ISCAS.1998.706981
  • Filename
    706981
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2190459