Exploration of energy-delay tradeoffs in digital circuit design

Modern VLSI design requires a tradeoff between circuit speed and power dissipation. Timing optimization methods typically lead to excessive power consumption. In this work, we explore the energy/performance design space in CMOS circuits, to find gate sizes which produce the lowest possible power for any specified circuit delay. The tradeoff between energy and performance is achieved by relaxing the timing of the circuit through downsizing of the cells, thus reducing the active energy dissipation. Our analysis method is based on the commonly used logical effort methodology, extended to model power as well as delay. We introduce the energy/delay gain (EDG) notation, which measures the energy reduction rate that is achievable for each delay increase that is acceptable by the designer, and the local EDG (LEDG) property, as a metric for choosing an operating point on the EDG curve, while avoiding excessively low marginal costs. The proposed analytical method is shown to be accurate when compared to simulation based numerical optimization, and orders of magnitude faster.