Modeling and simulation of jitter in phase-locked loops due to substrate noise

This paper presents a methodology to simulate, at the system-level, substrate noise coupling to phase-locked loop (PLL) circuits. Macro models of the noise coupling to the PLL are proposed based on the concept of an impulse sensitivity function (ISF). A system-level simulation is implemented using Verilog-A and achieves significant advantage, namely 50 times speed enhancement over circuit-level simulation. Furthermore, a period histogram and its variations are considered as metrics to analyze the substrate noise effects on the PLL and the simulation method is verified by comparison with the measured data of period histogram variation patterns.