Device design tradeoffs for 55v ldmos driver embedded in 0.18 micron platform

Author

Klein, Nathanaelle ; Levin, Sharon ; Fleishon, Gal ; Levy, Sagy ; Eyal, Alon ; Shapira, Shye

Author_Institution

Tower Semicond., Migdal Ha´´Emek, Israel

fYear

2008

fDate

3-5 Dec. 2008

Firstpage

736

Lastpage

740

Abstract

We describe the optimization of a 55 V breakdown LDMOS embedded in a 0.18 micron based power management platform. The devices self aligned structure allow the accessing low RdsOn values of 50 mohm mm². We focus on the effects of gate poly over STI overlap which can increase the breakdown voltage by 10 V and reduce maximum substrate current 5 fold while not affecting the specific RdsOn.

Keywords

CMOS integrated circuits; driver circuits; electric breakdown; integrated circuit design; low-power electronics; Integrated power CMOS platforms; LDMOS driver; based power management platform; breakdown voltage; maximum substrate current; self aligned structure device; size 0.18 micron; voltage 55 V; Aluminum; Breakdown voltage; CMOS logic circuits; CMOS process; Energy management; Immune system; Implants; Logic devices; Metal-insulator structures; Poles and towers; Breakdown Voltage (BVDSS); Hot Carrier Injection (HCI); Lateral Diffused MOS (LDMOS); ON Resistance (RdsOn); TCAD;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Electronics Engineers in Israel, 2008. IEEEI 2008. IEEE 25th Convention of

Conference_Location

Eilat

Print_ISBN

978-1-4244-2481-8

Electronic_ISBN

978-1-4244-2482-5

Type

conf

DOI

10.1109/EEEI.2008.4736631

Filename

4736631