Behavioural modeling and simulation of a switched-current phase locked loop

In this paper we describe the design approach of a phase locked loop (PLL) based on a novel switched-current (SI) architecture using behavioural models written in MAST. Simulations demonstrate the performance of the design at a high level and are used to optimize the behaviour of the loop response with regard to design specifications. The modeling approach is explained, from the basic building blocks used in the SI methodology through to more abstract models of the system architecture. The advantage of using behavioural models is highlighted with the ability to carry out parametric analysis and statistical analysis to investigate tolerances, adherence to specifications and parameter variations. The resulting simulations are consistent with transistor level simulation results, but several orders of magnitude faster. The resulting design achieves a performance that is comparable with designs using current techniques but with significantly reduced area.