DocumentCode
2191130
Title
Efficient Interpolation Architecture for Soft-Decision Reed-Solomon Decoding
Author
Zhu, Jiangli ; Zhang, Xinmiao
Author_Institution
Department of Electrical Engineering and Computer Science, Case Western Reserve University, 10900 Euclid Ave., Cleveland, OH 44106-7071
fYear
2007
fDate
17-19 Oct. 2007
Firstpage
663
Lastpage
668
Abstract
Reed-Solomon (RS) codes can be found in many digital communication and storage systems. Recently, significant advancements have been made on algebraic soft-decision decoding (ASD) of RS codes. Among the ASD algorithms with practical multiplicity assignment scheme, the bit-level generalized minimum distance (BGMD) decoding algorithm can achieve similar or higher coding gain with lower complexity. Interpolation is one of the major steps in ASD algorithms. The newly proposed Lee-O´Sullivan (LO) interpolation algorithm is computationally simple, and thus can potentially lead to practical high-speed and small-area hardware implementation of the interpolation step. In this paper, a novel interpolation architecture for the BGMD decoder based on the LO algorithm is proposed. By exploiting the characteristics of the LO algorithm and the multiplicity assignment scheme in the BGMD decoder, the proposed interpolation architecture for a (255, 239) RS code can achieve 15% higher efficiency in terms of speed over area ratio than prior efforts.
Keywords
Character generation; Computer architecture; Decoding; Digital communication; Hardware; Interpolation; Polynomials; Reed-Solomon codes; Variable speed drives; Very large scale integration; Reed-Solomon codes; VLSI architecture; algebraic soft-decision decoding; interpolation;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems, 2007 IEEE Workshop on
Conference_Location
Shanghai, China
ISSN
1520-6130
Print_ISBN
978-1-4244-1222-8
Electronic_ISBN
1520-6130
Type
conf
DOI
10.1109/SIPS.2007.4387628
Filename
4387628
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