Dependable testing of compactor MISR: an imperceptible problem?

Shows that current techniques that use BISTs for testing CUTs often make it impossible to distinguish which one is faulty: a CUT or a MISR. The paper shows a number of additional benefits following from making use of BIST to test chips, FPGA circuits etc., if the only effect were that the testing of an MISR would confirm credibly the correctness of the MISR. Furthermore, the paper proposes such modification of the MISR compactor structure that it makes possible to obtain reliable results of testing. Additionally, an effective technique of testing such compactor is presented and a minimal number of test clock cycles that is required for full testing its correctness is determined.