Title :
RESPIN++ - deterministic embedded test
Author :
Schäfer, Lars ; Dorsch, Rainer ; Wunderlich, Hans-Joachim
Author_Institution :
Stuttgart Univ., Germany
Abstract :
RESPIN++ is a deterministic embedded test method tailored to system chips, which implement scan test at core level. The scan chains of one core of the system-on-a-chip are reused to decompress the patterns for another core. To implement the RESPIN++ test architecture only a few gates need to be added to the test wrapper. This will not affect the critical paths of the system. The RESPIN++ method reduces both test data volume and test application time up to one order of magnitude per core compared to storing compacted test patterns on the ATE. If several cores may be tested concurrently, test data volume and test application time for the complete system test may be reduced even further. This paper presents the RESPIN++ test architecture and a compression algorithm for the architecture.
Keywords :
automatic testing; encoding; integrated circuit testing; logic testing; system-on-chip; RESPIN++ test architecture; core level scan test; deterministic embedded test method; encoding algorithm; system chip testing; system-on-a-chip; test application time reduction; test data volume reduction; test pattern compaction; test wrapper; Bandwidth; Compression algorithms; Costs; Decoding; Encoding; Pins; Productivity; System testing; System-on-a-chip; Timing;
Conference_Titel :
Test Workshop, 2002. Proceedings. The Seventh IEEE European
Print_ISBN :
0-7695-1715-3
DOI :
10.1109/ETW.2002.1029637
