DocumentCode
2191735
Title
Threaded multiple path execution
Author
Wallace, Steven ; Calder, Brad ; Tullsen, Dean M.
Author_Institution
Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
fYear
1998
fDate
27 Jun-1 Jul 1998
Firstpage
238
Lastpage
249
Abstract
This paper presents Threaded Multi-Path Execution (TME), which exploits existing hardware on a Simultaneous Multithreading (SMT) processor to speculatively execute multiple paths of execution. When there are fewer threads in an SMT processor than hardware contexts, threaded multi-path execution uses spare contexts to fetch and execute code along the less likely path of hard-to-predict branches. This paper describes the hardware mechanisms needed to enable an SMT processor to efficiently spawn speculative threads for threaded multi-path execution. The Mapping Synchronization Bus is described which enables the spawning of these multiple paths. Policies are examined for deciding which branches to fork, and for managing competition between primary and alternate path threads for critical resources. Our results show that TME increases the single program performance of an SMT with eight thread contexts by 14%-23% on average, depending on the misprediction penalty, for programs with a high misprediction rate
Keywords
parallel architectures; performance evaluation; synchronisation; hard-to-predict branches; mapping synchronization bus; simultaneous multithreading processor; single program performance; threaded multiple path execution; Accuracy; Computer science; Electronic switching systems; Multithreading; Pattern recognition; Pipelines; Resource management; Surface-mount technology; Throughput; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Architecture, 1998. Proceedings. The 25th Annual International Symposium on
Conference_Location
Barcelona
ISSN
1063-6897
Print_ISBN
0-8186-8491-7
Type
conf
DOI
10.1109/ISCA.1998.694778
Filename
694778
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