• DocumentCode
    2191863
  • Title

    CSDA: An Adaptive Data Storage Strategy for Predictive Branch Path on Multi-Core Architecture

  • Author

    Jun, Zhang ; Kui-Zhi, Mei ; Ji-Zhong, Zhao

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Xi´´an JiaoTong Univ., Xi´´an, China
  • fYear
    2010
  • fDate
    June 29 2010-July 1 2010
  • Firstpage
    1695
  • Lastpage
    1702
  • Abstract
    “Memory Wall” has already become the chief barrier for processor performance promotion. Cache pollution caused by speculative execution of memory instructions in predictive path may impact the performance of processor seriously. This paper proposes an adaptive storage frame to filter pollution data from predictive path based on confidence estimation mechanism for multi-core architecture, called CSDA. Firstly, CSDA makes use of confidence estimation mechanism to separate out the more likely mis-predicted paths from all predictive paths adaptively. Secondly, CSDA divides all memory reference instructions in low confidence predictive path into pre-fetching type and pollution type according to the low confidence pollution type memory reference recognition history table. Thirdly, a special low priority Load/Store queue is created for these pollution type memory reference instructions, and pollution data cache is used to store pollution data. Finally, CSDA may alleviate the negative effect of cache pollution data, and promote the effective memory bandwidth. Simulation result indicates that, in dual-core configuration, CSDA could avoid most cache pollution and upgrade performance. Relative to the baseline architecture, miss rate of D-Cache reduces from 9% to 23%, average 17%. Miss rate reduction of L2 cache ranges from 1.02% to 14.39%, average 5.67%. IPC improves from 0.19% to 5.59%, average 2.21%.
  • Keywords
    cache storage; multiprocessing systems; CSDA; adaptive data storage strategy; cache pollution; confidence estimation mechanism; load/store queue; memory reference instructions; memory wall; multi-core architecture; pollution data cache; predictive branch path; Delay; Estimation; History; Indexes; Multicore processing; Pollution; Registers; Adaptation; Cache Pollution; Chip Multi-core; Confidence Estimation; Memory System;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer and Information Technology (CIT), 2010 IEEE 10th International Conference on
  • Conference_Location
    Bradford
  • Print_ISBN
    978-1-4244-7547-6
  • Type

    conf

  • DOI
    10.1109/CIT.2010.298
  • Filename
    5577962