Title :
Multilevel test structures for metal CMP integration application to Cu/SiO2 damascene interconnect
Author :
Fayolle, M. ; Gayet, P. ; Morand, Y.
Author_Institution :
Lab d´´Electron. et de Technol. de l´´Inf., CEA, Centre d´´Etudes Nucleaires de Grenoble, France
Abstract :
This paper presents a method to evaluate the metal CMP impact on the performance of multilevel interconnect. For this purpose specific two metal level test structures have been defined, after a brief description of these structures, we present the results obtained on a Cu/SiO2 dual damascene architecture. It is shown that the upper metal yield is drastically degraded by the underlying metal layer patterns. Therefore a two levels study is essential to integrate a metal CMP in a multilevel metallization
Keywords :
chemical mechanical polishing; copper; integrated circuit interconnections; integrated circuit testing; silicon compounds; Cu-SiO2; Cu/SiO2 dual damascene interconnect; metal CMP; multilevel metallization; process integration; test structure; Copper; Degradation; Electric resistance; Electric variables measurement; Electrical resistance measurement; Geometry; Metallization; Space exploration; Surfaces; Testing;
Conference_Titel :
Interconnect Technology Conference, 2000. Proceedings of the IEEE 2000 International
Conference_Location :
Burlingame, CA
Print_ISBN :
0-7803-6327-2
DOI :
10.1109/IITC.2000.854271
