Fast result normalization in FP adder

Floating-point adders use double-path structure to reduce the latency. In the present implementation there are two paths: NORMALIZING and ROUNDING. The NORMALIZING path includes significand adder, normalization shift amount generator, normalizer, result exponent correction adder. The MSBs of the shift amount for result normalization are anticipated, and the LSBs of the shift amount are detected. Both parts of the shift amount generator take into account the maximum shift amount implied by the ANSI/IEEE Standard No 754. That makes possible to implement gradual underflow mode in hardware with small area and latency overhead. The presented leading zeroes anticipation analyzes input operand rather than the summands of the adder. A method of inexact anticipation correction has been proposed that delivers the exact result without extra logical levels. Area and critical paths have been evaluated.