Performance and Power Consumption Analysis of DVFS-Enabled H.264 Decoder on Heterogeneous Multi-Core Platform

Power consumption becomes a very important criterion for the portable embedded devices and, therefore, many Dynamic Voltage/Frequency Scaling (DVFS) techniques have been introduced. This paper is trying to break down and analyze the power consumed by three main components, DSP logic, local memory, and the external DDR2, of a multi-core SoC platform. There are four configurations for this SoC platform: one DSP with full and half clock rates and two DSP´s with full and half clock rates. The DSP´s in the SoC are clone in the hardware architecture and execute the same H.264/AVC decoder software in all scenarios. With this breakdown, we can figure out the key factors for energy saving and further offer some valuable suggestions for the power management and embedded multi-core SoC designs.