DocumentCode
2192246
Title
New method to study unlanded via architecture. Application to advanced interconnects: Al with low k and copper dual damascene
Author
Gayet, Ph ; Lair, C. ; Vegt, E. V d
Author_Institution
STMicroelectron., Crolles, France
fYear
2000
fDate
2000
Firstpage
73
Lastpage
75
Abstract
This paper describes a new test structure developed to study unlanded vias. The limitation of conventional chains to characterize vias is shown. The new structures enabled us to improve product yield in a 0.18 μm technology using HSQ and aluminum interconnects. Finally, it is emphasized that it is very useful to compare different copper dual damascene architectures
Keywords
CMOS integrated circuits; aluminium; copper; integrated circuit interconnections; integrated circuit yield; 0.18 mum; Al; CMOS; Cu; advanced interconnects; dual damascene; product yield; unlanded via architecture; Aluminum; Artificial intelligence; CMOS technology; Circuit testing; Copper; Dielectrics; Integrated circuit interconnections; Monitoring; Production; Semiconductor device testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Interconnect Technology Conference, 2000. Proceedings of the IEEE 2000 International
Conference_Location
Burlingame, CA
Print_ISBN
0-7803-6327-2
Type
conf
DOI
10.1109/IITC.2000.854286
Filename
854286
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